Global majors such as Qualcomm<\/a>, Intel<\/a>, Mediatek, Infineon<\/a>, and Texas Instruments have their research and development in India which contribute in the development of their chipsets.
\"The government is deliberating on a new semiconductor design-linked incentive scheme which envisages financial and infrastructure support for Indian MSMEs and startups right through the ideate stage to production stage. As and when these startups start producing and selling chips in the market, they shall also avail additional incentives under the scheme on their net sales turnover,\" an official source told PTI.
Minister of State for Electronics<\/a> and IT Rajeev Chandrasekhar<\/a> last week had said that the government would host a conference of semiconductor companies in November to discuss India's policy<\/a> roadmap in the segment.
\"It is a great initiative which will leverage India's strength to make an impact in the field of design of semiconductors. We can target to have 25 plus fabless companies in the next few years which will make a substantial impact in the global semiconductor market,\" industry body IESA<\/a> chairman Rajeev Khushu said.
The semiconductor design is the main driver of revenues that electronic chip companies earn from sale of their high end components.<\/body>","next_sibling":[{"msid":87280847,"title":"Samsung to finalise US fab investment","entity_type":"ARTICLE","link":"\/news\/samsung-to-finalise-us-fab-investment\/87280847","category_name":null,"category_name_seo":"telecomnews"}],"related_content":[],"msid":87281051,"entity_type":"ARTICLE","title":"Govt planning semiconductor design-linked incentive policy","synopsis":"Global majors such as Qualcomm, Intel, Mediatek, Infineon, and Texas Instruments have their research and development in India which contribute in the development of their chipsets.","titleseo":"telecomnews\/govt-planning-semiconductor-design-linked-incentive-policy","status":"ACTIVE","authors":[],"analytics":{"comments":0,"views":562,"shares":0,"engagementtimems":2671000},"Alttitle":{"minfo":""},"artag":"PTI","artdate":"2021-10-26 17:58:35","lastupd":"2021-10-26 19:54:00","breadcrumbTags":["semiconductor manufacturing","semiconductor design-linked incentive policy","policy","Minister of State for Electronics","infineon","intel","iesa","meity","qualcomm","Rajeev Chandrasekhar"],"secinfo":{"seolocation":"telecomnews\/govt-planning-semiconductor-design-linked-incentive-policy"}}" data-news_link="//www.iser-br.com/news/govt-planning-semiconductor-design-linked-incentive-policy/87281051">