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<\/span><\/figcaption><\/figure>By Stephen Nellis
<\/strong>
Research teams at Intel Corp<\/a> on Saturday unveiled work that the company believes will help it keep speeding up and shrinking computing chips over the next ten years, with several technologies aimed at stacking parts of chips on top of each other.

Intel<\/a>'s Research Components Group introduced the work in papers at an international conference being held in San Francisco. The Silicon Valley company is working to regain a lead in making the smallest, fastest chips that it has lost in recent years to rivals like Taiwan Semiconductor Manufacturing Co and Samsung Electronics Co Ltd.

While Intel CEO Pat Gelsinger has laid out commercial plans aimed at regaining that lead by 2025, the research work unveiled Saturday gives a look into how Intel plans to compete beyond 2025.

One of the ways Intel is packing more computing power into chips by stacking up \"tiles\" or \"chiplets\" in three dimensions rather than making chips all as one two-dimension piece. Intel showed work Saturday that could allow for 10 times as many connections between stacked tiles, meaning that more complex tiles can be stacked on top of one another.

But perhaps the biggest advance showed Saturday was a research paper demonstrating a way to stack transistors - tiny switches that form the most basic building bocks of chips by representing the 1s and 0s of digital logic - on top of one another.

Intel believes the technology will yield a 30% to 50% increase in the number of transistors it can pack into a given area on a chip<\/a>. Raising the number of transistors is the main reason chips have consistently gotten faster over the past 50 years.

\"By stacking the devices<\/a> directly on top of each other, we're clearly saving area,\" Paul Fischer, director and senior principal engineer of Intel's Components Research Group told Reuters in an interview. \"We're reducing interconnect lengths and really saving energy, making this not only more cost efficient, but also better performing.\"

<\/body>","next_sibling":[{"msid":88227260,"title":"Realme rolls out UI 3.0 early access for some phones","entity_type":"ARTICLE","link":"\/news\/realme-rolls-out-ui-3-0-early-access-for-some-phones\/88227260","category_name":null,"category_name_seo":"telecomnews"}],"related_content":[],"msid":88234861,"entity_type":"ARTICLE","title":"Intel shows research for packing more computing power into chips beyond 2025","synopsis":"Intel's Research Components Group introduced the work in papers at an international conference being held in San Francisco. The Silicon Valley company is working to regain a lead in making the smallest, fastest chips that it has lost in recent years to rivals like Taiwan Semiconductor Manufacturing Co and Samsung Electronics Co Ltd.","titleseo":"telecomnews\/intel-shows-research-for-packing-more-computing-power-into-chips-beyond-2025","status":"ACTIVE","authors":[],"analytics":{"comments":0,"views":268,"shares":0,"engagementtimems":969000},"Alttitle":{"minfo":""},"artag":"Reuters","artdate":"2021-12-12 10:30:07","lastupd":"2021-12-12 10:34:29","breadcrumbTags":["chip manufacturing","intel","chip","chipmaking","chip maker","devices","Intel Corp","semiconductors"],"secinfo":{"seolocation":"telecomnews\/intel-shows-research-for-packing-more-computing-power-into-chips-beyond-2025"}}" data-authors="[" "]" data-category-name="" data-category_id="" data-date="2021-12-12" data-index="article_1">

英特尔展示了包装更多的计算能力研究芯片超出2025

英特尔的研究组件集团在论文中介绍了工作在一个国际会议在旧金山举行。这家硅谷公司正在努力重新获得领先的最小、最快的芯片,它已经失去了近年来竞争对手台湾半导体制造公司和三星电子有限公司。

  • 更新于2021年12月12日,在34是坚持
阅读: 100年行业专业人士
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斯蒂芬·内尔尼斯
研究团队英特尔(intc . o:行情)周六公布的工作,该公司认为这将有助于保持加速和减少计算芯片在未来十年,与几个技术旨在叠加部分芯片上。

英特尔在论文研究组件组介绍了工作在一个国际会议在旧金山举行。这家硅谷公司正在努力重新获得领先的最小、最快的芯片,它已经失去了近年来竞争对手台湾半导体制造公司和三星电子有限公司。

广告
虽然英特尔首席执行官Pat Gelsinger已经制定了商业计划,旨在恢复,到2025年,周六公布的研究工作给出了调查英特尔计划如何竞争超越2025人。

英特尔的方法之一是包装更多的计算能力芯片通过叠加“瓷砖”或“chiplets”在三维空间中而不是芯片制造所有二维块。英特尔显示周六工作,可以让十倍叠加瓷砖之间的联系,这意味着更复杂的瓷砖可以堆叠在彼此之上。

但也许最大的进步显示周六研究论文展示一种堆栈晶体管——小开关形式最基本的建筑烈性黑啤酒芯片代表0和1的数字逻辑,在另一个之上。

英特尔认为,这项技术将产量增加30%到50%的晶体管数量可以包成一个特定区域芯片。提高芯片的晶体管数量是主要原因一直得到更快的在过去的50年。

“通过叠加设备直接在彼此之上,我们明显节省面积,”保罗•菲舍尔董事和高级首席工程师英特尔组件的研究小组在一次采访中对路透表示。“我们真的降低互连长度和节约能源,这不仅更高效,而且更好的表现。”

  • 发布于2021年12月12日上午10:30坚持
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  • 英特尔展示了包装更多的计算能力研究芯片超出2025
\"\"
<\/span><\/figcaption><\/figure>By Stephen Nellis
<\/strong>
Research teams at Intel Corp<\/a> on Saturday unveiled work that the company believes will help it keep speeding up and shrinking computing chips over the next ten years, with several technologies aimed at stacking parts of chips on top of each other.

Intel<\/a>'s Research Components Group introduced the work in papers at an international conference being held in San Francisco. The Silicon Valley company is working to regain a lead in making the smallest, fastest chips that it has lost in recent years to rivals like Taiwan Semiconductor Manufacturing Co and Samsung Electronics Co Ltd.

While Intel CEO Pat Gelsinger has laid out commercial plans aimed at regaining that lead by 2025, the research work unveiled Saturday gives a look into how Intel plans to compete beyond 2025.

One of the ways Intel is packing more computing power into chips by stacking up \"tiles\" or \"chiplets\" in three dimensions rather than making chips all as one two-dimension piece. Intel showed work Saturday that could allow for 10 times as many connections between stacked tiles, meaning that more complex tiles can be stacked on top of one another.

But perhaps the biggest advance showed Saturday was a research paper demonstrating a way to stack transistors - tiny switches that form the most basic building bocks of chips by representing the 1s and 0s of digital logic - on top of one another.

Intel believes the technology will yield a 30% to 50% increase in the number of transistors it can pack into a given area on a chip<\/a>. Raising the number of transistors is the main reason chips have consistently gotten faster over the past 50 years.

\"By stacking the devices<\/a> directly on top of each other, we're clearly saving area,\" Paul Fischer, director and senior principal engineer of Intel's Components Research Group told Reuters in an interview. \"We're reducing interconnect lengths and really saving energy, making this not only more cost efficient, but also better performing.\"

<\/body>","next_sibling":[{"msid":88227260,"title":"Realme rolls out UI 3.0 early access for some phones","entity_type":"ARTICLE","link":"\/news\/realme-rolls-out-ui-3-0-early-access-for-some-phones\/88227260","category_name":null,"category_name_seo":"telecomnews"}],"related_content":[],"msid":88234861,"entity_type":"ARTICLE","title":"Intel shows research for packing more computing power into chips beyond 2025","synopsis":"Intel's Research Components Group introduced the work in papers at an international conference being held in San Francisco. The Silicon Valley company is working to regain a lead in making the smallest, fastest chips that it has lost in recent years to rivals like Taiwan Semiconductor Manufacturing Co and Samsung Electronics Co Ltd.","titleseo":"telecomnews\/intel-shows-research-for-packing-more-computing-power-into-chips-beyond-2025","status":"ACTIVE","authors":[],"analytics":{"comments":0,"views":268,"shares":0,"engagementtimems":969000},"Alttitle":{"minfo":""},"artag":"Reuters","artdate":"2021-12-12 10:30:07","lastupd":"2021-12-12 10:34:29","breadcrumbTags":["chip manufacturing","intel","chip","chipmaking","chip maker","devices","Intel Corp","semiconductors"],"secinfo":{"seolocation":"telecomnews\/intel-shows-research-for-packing-more-computing-power-into-chips-beyond-2025"}}" data-news_link="//www.iser-br.com/news/intel-shows-research-for-packing-more-computing-power-into-chips-beyond-2025/88234861">